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////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////////
// smpram.v: Switchable multiported-RAM: register-based, XOR-based,               //
//           register-based LVT, SRAM-based binary & one-hot I-LVT                //
//                                                                                //
//    Author: Ameer M. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com)    //
// Switchable SRAM-based Multi-ported RAMs; University of British Columbia, 2014  //
////////////////////////////////////////////////////////////////////////////////////

`include "utils.vh"

module smpram
 #(  parameter MEMD  = 16   ,    // memory depth
     parameter DATW  = 32   ,    // data width
     parameter nRPN  = 2    ,    // number of reading ports in normal   mode
     parameter nWPN  = 2    ,    // number of writing ports in normal   mode
     parameter nRPE  = nRPN ,    // number of reading ports in extended mode
     parameter nWPE  = nWPN ,    // number of writing ports in extended mode
     parameter ARCH  = ""   ,    // implementation type: REG, XOR, LVTREG, LVTBIN, LVT1HT, AUTO
     parameter BYPS  = "RAW",    // Bypassing type: NON, WAW, RAW, RDW
                                    // WAW: Allow Write-After-Write (need to bypass feedback ram)
                                    // RAW: new data for Read-after-Write (need to bypass output ram)
                                    // RDW: new data for Read-During-Write
     parameter FILE = "init_ram" // initialization file, optional
  )( input                              clk  ,  // clock
     input                              ext  ,  // extended mode
     input       [nWPN-1:0            ] WEnb ,  // write enable for each writing port
     input       [`log2(MEMD)*nWPN-1:0] WAddr,  // write addresses - packed from nWPN write ports
     input       [DATW       *nWPN-1:0] WData,  // write data - packed from nWPN read ports
     input       [`log2(MEMD)*nRPE-1:0] RAddr,  // read  addresses - packed from nRPE  read  ports
     output wire [DATW       *nRPE-1:0] RData); // read  data - packed from nRPE read ports

  localparam ADDRW = `log2(MEMD); // address width

  // Auto calculation of best method when ARCH="AUTO" is selected.
  localparam l2nW     = `log2(nWPN);
  localparam nBitsXOR = DATW*(nWPN-1);
  localparam nBitsBIN = l2nW*(nWPN+nRPN-1);
  localparam nBits1HT = (nWPN-1)*(nRPN+1);
  localparam AUTOARCH = ( (nBits1HT<=nBitsXOR) && (nBits1HT<=nBitsBIN) ) ? "LVT1HT" : ( (nBitsBIN<=nBitsXOR) ? "BIN" : "XOR" );
  // if ARCH is not one of known types (REG, XOR, LVTREG, LVTBIN, LVT1HT) choose auto (best) ARCH
  localparam iARCH    = ((ARCH!="REG")&&(ARCH!="XOR")&&(ARCH!="LVTREG")&&(ARCH!="LVTBIN")&&(ARCH!="LVT1HT")) ? AUTOARCH : ARCH;

  // Bypassing indicators
  localparam WAWB =  BYPS!="NON"               ; // allow Write-After-Write (need to bypass feedback ram)
  localparam RAWB = (BYPS=="RAW")||(BYPS=="RDW"); // new data for Read-after-Write (need to bypass output ram)
  localparam RDWB =  BYPS=="RDW"               ; // new data for Read-During-Write


  // generate and instantiate RAM with specific implementation
  generate
    if (nWPN==1) begin
      // instantiate multiread RAM
      mrram            #( .MEMD   (MEMD      ),  // memory depth
                          .DATW  (DATW       ),  // data width
                          .nRP   (nRPE       ),  // number of reading ports
                          .BYPS  (RDWB?2:RAWB),  // bypass? 0:none; 1:single-stage; 2:two-stages
                          .FILE  (FILE       ))  // initialization file, optional
      mrram_ins         ( .clk   (clk        ),  // clock                                         - in
                          .WEnb  (WEnb       ),  // write enable  (1 port)                        - in
                          .WAddr (WAddr      ),  // write address (1 port)                        - in : [`log2(MEMD)     -1:0]
                          .WData (WData      ),  // write data    (1 port)                        - in : [DATW            -1:0]
                          .RAddr (RAddr      ),  // read  addresses - packed from nRPN read ports - in : [`log2(MEMD)*nRPN-1:0]
                          .RData (RData      )); // read  data      - packed from nRPN read ports - out: [DATW       *nRPN-1:0]
    end
    else if (iARCH=="REG"   ) begin
      // instantiate multiported register-based RAM
      mpram_reg    #( .MEMD  (MEMD ),  // memory depth
                      .DATW  (DATW ),  // data width
                      .nRP   (nRPE ),  // number of reading ports
                      .nWP   (nWPN ),  // number of writing ports
                      .RDWB  (RDWB ),  // provide new data when Read-During-Write?
                      .FILE  (FILE ))  // initializtion file, optional
      mpram_reg_ref ( .clk   (clk  ),  // clock
                      .WEnb  (WEnb ),  // write enable for each writing port             - in : [nWPN-1:0            ]
                      .WAddr (WAddr),  // write addresses - packed from nWPN write ports - in : [`log2(MEMD)*nWPN-1:0]
                      .WData (WData),  // write data      - packed from nRPN read  ports - in : [DATW       *nWPN-1:0]
                      .RAddr (RAddr),  // read  addresses - packed from nRPN read  ports - in : [`log2(MEMD)*nRPN-1:0]
                      .RData (RData)); // read  data      - packed from nRPN read  ports - out: [DATW       *nRPN-1:0]
    end
    else if (iARCH=="XOR"   ) begin
      // instantiate XOR-based multiported RAM
      mpram_xor    #( .MEMD  (MEMD ),  // memory depth
                      .DATW  (DATW ),  // data width
                      .nRP   (nRPE ),  // number of reading ports
                      .nWP   (nWPN ),  // number of writing ports
                      .WAWB  (WAWB ), // allow Write-After-Write (need to bypass feedback ram)
                      .RAWB  (RAWB ), // new data for Read-after-Write (need to bypass output ram)
                      .RDWB  (RDWB ), // new data for Read-During-Write
                      .FILE  (FILE ))  // initializtion file, optional
      mpram_xor_ins ( .clk   (clk  ),  // clock
                      .WEnb  (WEnb ),  // write enable for each writing port             - in : [nWPN-1:0            ]
                      .WAddr (WAddr),  // write addresses - packed from nWPN write ports - in : [`log2(MEMD)*nWPN-1:0]
                      .WData (WData),  // write data      - packed from nRPN read  ports - in : [DATW       *nWPN-1:0]
                      .RAddr (RAddr),  // read  addresses - packed from nRPN read  ports - in : [`log2(MEMD)*nRPN-1:0]
                      .RData (RData)); // read  data      - packed from nRPN read  ports - out: [DATW       *nRPN-1:0]
    end
    else begin
      // instantiate a multiported RAM with onehot-coded SRAM LVT
      mpram_lvt    #( .MEMD  (MEMD ),  // memory depth
                      .DATW  (DATW ),  // data width
                      .nRPN  (nRPN ),  // number of reading ports in normal   mode
                      .nWPN  (nWPN ),  // number of writing ports in normal   mode
                      .nRPE  (nRPE ),  // number of reading ports in extended mode
                      .nWPE  (nWPE ),  // number of writing ports in extended mode
                      .LVTA  (iARCH),  // LVT architecture type: LVTREG, LVTBIN, LVT1HT
                      .WAWB  (WAWB ),  // allow Write-After-Write (need to bypass feedback ram)
                      .RAWB  (RAWB ),  // new data for Read-after-Write (need to bypass output ram)
                      .RDWB  (RDWB ),  // new data for Read-During-Write
                      .FILE  (FILE ))  // initializtion file, optional
      mpram_lvt_ins ( .clk   (clk  ),  // clock
                      .ext   (ext  ),  // extended mode
                      .WEnb  (WEnb ),  // write enable for each writing port             - in : [nWPN-1:0            ]
                      .WAddr (WAddr),  // write addresses - packed from nWPN write ports - in : [`log2(MEMD)*nWPN-1:0]
                      .WData (WData),  // write data      - packed from nRPN read  ports - in : [DATW       *nWPN-1:0]
                      .RAddr (RAddr),  // read  addresses - packed from nRPN read  ports - in : [`log2(MEMD)*nRPN-1:0]
                      .RData (RData)); // read  data      - packed from nRPN read  ports - out: [DATW       *nRPN-1:0]
    end
  endgenerate

endmodule

